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Hardware·2 min read

AMD Epyc Venice-X Brings Back 3D V-Cache With 5.3 GHz Clocks

AMD is reviving its cache-heavy Epyc X line after three years. Venice-X offers up to 96 cores, over 1 GB of L3 and 5.3 GHz clocks, but ships only in late 2027.

Close-up of an AMD Epyc server processor with stacked cache chiplets on a dark background.
Image: theregister
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AMD is bringing back its cache-packed Epyc X processors. The HPC-focused Venice-X parts will offer up to 96 cores and use 3D V-Cache stacking to triple L3 cache density to more than a gigabyte per socket. They won't arrive soon: AMD expects them to begin shipping in the second half of 2027.

First teased at CES earlier this year, the chips target latency-sensitive technical and scientific workloads such as computational fluid dynamics and electronic design automation (EDA). AMD uses X-series Epycs itself for EDA jobs like functional verification, which simulates silicon to confirm it behaves as designed. According to AMD Fellow Phil Steinke, keeping more of the model in cache means cores spend less time waiting for data to move to and from system memory.

Same cache, much higher clocks

Each of up to eight CPU dies is bonded to a 96 MB SRAM tile, giving 144 MB of L3 per chiplet and 1,152 MB per socket. That matches the Genoa-X parts Venice-X replaces. Clock speeds are where the change lies: Venice-X reaches 5.3 GHz, against 3.7 GHz for Genoa-X.

The jump comes from packaging. Earlier designs stacked SRAM on top of the compute chiplet, which trapped heat and limited boost clocks. With the Zen 5 generation AMD moved the SRAM tile beneath the compute die, letting chips run hotter and faster. Gamers saw this first in Ryzen 9000 processors; Epyc gets it only now.

Madhu Rangarajan, who runs AMD's compute and enterprise AI products business, said customers previously had to choose between high frequency and 3D V-Cache. He expects Venice-X to be "much bigger in HPC" than earlier generations because that trade-off is gone.

Why a three-year gap

The previous X-series chips launched in 2023, and there was no Turin-X in the 5th-gen Epyc line-up in late 2024. Rangarajan said this was deliberate: the enterprise HPC market moves at a slower cadence, so AMD isn't doing an X part every generation.

AMD could in theory have fused off cores on a 256-core Venice to reach a similar cache-per-core ratio, as it did with the 16-core Epyc 9175F and its 512 MB of cache. But Rangarajan said that route would cap Fmax at 4.1 GHz rather than 5.3 GHz. "For the first time, you can get the larger L3 in our highest frequency part," he said.

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