Oak Ridge launches IBM-AMD quantum-HPC error correction testbed

AMD Versal SoCs complete the setup, providing low-latency control, readout and decoding for the quantum circuitry. ORNL says this puts the infrastructure needed for error correction into a single environment and opens it to more researchers than before.

Why it matters

Fault-tolerant quantum computers have long seemed a decade away, but ORNL points to notable progress in recent years, including early demonstrations of shielding quantum information from environmental noise that destroys fragile quantum states. QSC director Travis Humble called solving error correction essential to making quantum computing a practical tool for scientific discovery.

IBM's Jay Gambetta said the question is no longer whether error correction works, but how to accelerate and optimize it. The platform, he said, will let researchers evaluate approaches and determine which architectures, software and workflows scale.

One approach IBM expects to explore is hierarchical error correction: an inner code protects qubits within a module, and an outer code wraps the inner code's logical qubits for a second layer of protection. IBM research suggests this could reach a trillion logical operations at a physical error rate of one in a thousand. Such codes depend on powerful classical compute, which the GPUs in a low-latency environment are meant to supply.

What comes next

Researchers will use the platform to develop and validate algorithms, workflows and applications for quantum-centric supercomputing, where QPUs, CPUs and GPUs work as one system. It is likely to feed into the DoE's Quantum Genesis Mission, including the recently announced Q Competition, which aims to deliver a system with 100 logical qubits able to run hundreds of millions of fault-tolerant operations. That follows an executive order from President Trump to develop a full-blown quantum system by 2028.