Neowine Patents Method to Boost HBM Yield by Discarding Bad TSVs

How the patent works

Neowine's approach provides more TSVs than needed from the start and simply routes around any that fail. The conventional fix inserts spare TSVs (RTSVs) and multiplexer switch circuits into every DRAM die. According to the company, that enlarges the die, complicates the memory-cell process and accumulates RC signal delay layer by layer, slowing operation.

Neowine instead concentrates the path-selecting switches in a single place, the bottom base (buffer) die. The DRAM dies stay unchanged, which limits die area and process burden, while signal control is handled in the base die's fine logic process. Adding more spare paths also lets the design cope with multiple faults, such as two adjacent lines shorting. The company says HBM process yields, which typically sit at 30–70%, could reach as high as the 99% range.

Timing with HBM4

Starting with sixth-generation HBM (HBM4), I/O paths double from 1,024 to 2,048, sharply raising TSV density. At the same time, memory makers are moving base dies from their own DRAM processes to foundries' leading-edge logic processes, which makes it easier to pack switch logic into the base die. CEO Lee Hyo-seung said the shift of base dies to logic foundry processes lines up well with the patent's approach.